|
Wednesday, November 2, 2005 |
| 7-9pm |
Reception & On-Site Registration at Hyatt |
|
Thursday, November 3,
2005 |
| 7:30-8:30am |
Continental
Breakfast |
| 8:30-9:30am |
Keynote
Address |
| 9:30-11:50am (including a 10-15 minutes coffee
break) |
Session A: Architectural/Functional
Verification
Organizer: Eli Almog, IBM
A.1 A
Study of Architecture Description Languages from a Model-based
Perspective
Prof. Wei Qin (Boston University)
A.2 An
Introduction to the Plasma Language
Brian Kahne, Pete Wilson,
and
Aseem Gupta (Freescale)
A.3
Embedded Processor Design and SW Tool Generation Using
LISA
Andreas Hoffmann (CoWare)
A.4
Verifying Configurable ISAs Described in Tensilica's Instruction
Extension (TIE) Language
Dhanendra Jani (Tensilica)
A.5
Processor Architecture Description Language for Test
Generation
Eli Almog (IBM) |
| 11:50am-1pm |
Lunch
Break |
| 1pm – 2:40pm |
Session B: Debug and Diagnosis
B.1
Diagnosing faulty functional units in processors by using
automatically generated test sets
P. Bernardi, E. Sanchez, M.
Schillaci, G. Squillero, M. Sonza Reorda
Dipartimento di Automatica
e
Informatica, Politecnico di Torino, Italy
B.2
Post-Verification Debugging of Hierarchical Designs
Moayad
Fahim Ali, University of Toronto
Sean Safarpour, University of
Toronto
Andreas Veneris, University of Toronto
Magdy S. Abadir,
Freescale Semiconductor
Rolf Drechsler, University of Bremen,
Germany
B.3 An
Investigation of Excitation Balance and Additional Mandatory Conditions
for the Diagnosis of Fortuitously Detected Defects
Jennifer
Lynn
Dworak,
Brown University
B.4
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor
Cores
P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza
Reorda
Politecnico di Torino, Dipartimento di Automatica e
Informatica,
Torino, Italy |
| Coffee Break |
| 3:50 pm – 4:30pm |
Session C: SAT applications
C.1
Language-driven Validation of Pipelined Processors using
Satisfiability Solvers
Prabhat Mishra Heon-Mo Koo Zhuo
Huang
University of Florida, Gainesville, FL
C.2
Bounded Invariant Checking of Partial Implementations using a
Structural SAT-Solver
Marc Herbstritt and Bernd
Becker
Albert-Ludwigs-University Freiburg, Germany
C.3 PaMira
– a Parallel SAT Solver with Knowledge Sharing
Tobias Schubert
Matthew Lewis Bernd Becker
Institute for Computer Science,
Albert-Ludwigs-University of Freiburg, Freiburg,
Germany |
| 4:30 – 5:45pm |
Session D: Microprocessor test, circuit marginality
and
speed binning
D.1 Is
IDDQ Test of Microprocessors Feasible?
Bin Xue and D. M. H.
Walker, Texas A&M University
D.2
Improved methods for Circuit Marginality, Speed Path &
Manufacturing
Defect Detection
Greg Czajkowski, Dave LaFollette, Paul R.
Zehr
Intel Corporation
D.3 A
study on speed binning with structural tests
Benjamin Lee, Jing
Zeng, Li-C. Wang, Magdy S. Abadir
UC-Santa barbara and
Freescale |
| 6-10pm |
Dinner and
Social Event |
|
November 4, Friday |
| 7:30 – 8:30am |
Continental
Breakfast |
| 8:30 – 9:45am |
Session E: Validation
E.1
Automated Extraction of Structural Information from SystemCbased IP
for Validation
David Berner, Institut de Recherche en
Informatique
et Systèmes Aléatoires, France
Hiren D. Patel, Virginia Polytechnic
and
State University
Deepak A. Mathaikutty, Virginia Polytechnic and
State
University
Sandeep K. Shukla, Virginia Polytechnic and State
University
E.2
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core
Processors
Paul R Zehr and Soohong Kim, Intel
Corporation
E.3
Automatic Generation of High Performance Embedded Memory Models for
PowerPC Microprocessors
Jayanta Bhadra, Freescale
Semiconductor
Magdy S. Abadir, Freescale Semiconductor
David
Burgess, Freescale Semiconductor
and Ekaterina Trofimova, Freescale
Semiconductor |
| 9:45am – 10am |
Coffee
Break |
| 10am – 11:40am |
Session F: High-level ATPG and
Verification
F.1 On PSL
Properties Re-use in SoC Design Flow Based on Transaction Level
Modeling
Nicola Bombieri, STMicroelectronics
Andrea Fedeli,
STMicroelectronics
Franco Fummi, University of Verona
F.2 A
Pseudo-Deterministic Functional ATPG based on EFSM
Traversing
G.
Di Guglielmo F. Fummi C. Marconcini G. Pravadelli
Dipartimento di
Informatica - Università di Verona, Italy
F.3
SEARCH-SPACE OPTIMIZATIONS FOR HIGH-LEVEL ATPG
Jorge Campos
and Hussain Al-Asaad
University of California—Davis
F.4 HW/SW
Co-Verification of a RISC CPU using Bounded Model
Checking
Daniel
Grosse, Ulrich Kuehne, Rolf Drechsler, University of
Bremen |
| 11:40 – 12:40pm |
Lunch
Break |
| 12:55 –
3pm |
Session E: Invited Presentations
E.1 3D
Packaging – Its impact and implications
T. M. Mak, Intel
Corporation
E.2
Equivalence Checking -- An Industry Perspective
Kei-Yong
Khoo,
Cadence Design Systems, Inc. (Verplex group)
E.3 A TDM
Test Scheduling Method for Network-on-Chip Systems
Mark Nolen,
Rabi Mahapatra and Ray Mercer, Texas A&M University
(Optional) E.4
Simulation data mining for functional TPG
Charles Wen and
Li-C. Wang, UC-Santa Barbara |
| 3pm-4:15pm |
Special session F: IJTAG
Organizer:Al
Crouch, Inovys
Speaker: Jason
Doege, Cadence
Speaker: Adam Ley and Glenn Woppmann,
Asset-InterTech
Speaker: Al Crouch, Inovys |
| 4:30 – 5:45pm |
Special session G: Sequential EQ
G.1 Using
sequential equivalence checking in a microprocessor design
flow
Brian Kahne, Magdy Abadir, Freescale Semiconductor
G.2
Sequential Equivalence Checking of RTL Models
Gagan
Hasteer,
Venkat Krishnaswamy and Nikhil Sharma, Calypto Design Systems
G.3
Seq-SAT - An Efficient Sequential Circuit SAT Solver and Its
Application to Sequential Equivalence Checking
Feng Lu, K.-T.
Cheng and L.C Wang, Department of ECE, University of California at
Santa
Barbara |
| 6pm |
Close | |
